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Homework answers / question archive / Consider the following the design example

Consider the following the design example. Analog signal x(t) is digitized using an analog to digital converter (ADC) and the output of ADC is captured by the help of a FPGA as shown in the figure below. Within FPGA and a low pass filter is designed using FIR filter structure. After FIR filter, a decimation block is used to reduce the sampling rate of system.

FPGA

®^{x(t)}ADC ®^{x(n)} ® FIR Filter ®^{y(n)} Decimator

Fig. 1: System block diagram

1. Consider the system detailed in Fig. 1.

i. What is the Nyquist frequency of system when the sampling frequency of ADC is 1OOMHz?

ii. Calculate the dynamic range when 10-bit ADC is used in the design. In order to have more than 110dB dynamic range, what should be the minimum number of bits of ADC?

2. Implement the given FIR filter to suppress the unwanted signal components. Sampling clock of 12-bit ADC is 1OOMHz and FPGA clock is also 1OOMHz. System should process ADC data in streaming way. FIR filter specifications:

- Low pass filter, passband frequency is DC-25MHz, stopband frequency 40MHz to 50MHz, passband attenuation <1dB and stopband attenuation is >55dB. Coefficient bit length is 8bit.

- Filter is design using MATLAB filter design toolbox and the following coefficients are obtained. Coefficients: [2, 14, 7, -28, 15, 132, 132, 15, -28, 7, 14, 2]

i. One possible implementation for the specified FIR filter with given coefficient set using symmetry property is given below. Using symmetry property, the number multipliers are reduced. Find the minimum bit length of signals a0, a1, a2, a3, a4, a5, p0, p1, p2, p3, p4, p5, pa0, pa1, pa2, pa3 and y[n].

x(n] x[n-1] x[n-2] x[n-3] x[n-4] x[n-5] x[n-6] …….. x[n-10] x[n-11]

®Z^{-1} ® Z^{-1} ® Z^{-1} ® Z^{-1} ® Z^{-1} ® Z^{-1} ® Z^{-1} ® Z^{-1} ®

x[n-11] x[n-10] x[n-9] x[n-8] x[n-7]

a0 a1 a2 a3 a4 a5

2 14 7 -28 15 132

P0 p1 p2 p3 p4 p5

Pa0 pa1 pa2

Pa3 y[n]

ii. Write a Verilog or VHDL module (with correct syntax) called symmetricFIR for the given filter design in the behavioral design style. An asynchronous active high CLR input signal is used to reset the internal signals. The module should be sensitive to rising edge of CLK input. LOAD input signal is used to load the filter coefficients.

iii. In order to remove the multipliers from the filter design, the coefficients are modified to following sets: Coefficients: [2, 16, 8, -32, 16, 128, 128, 16, -32, 8, 16, 2]

How the given FIR filter with modified coefficient set can be implemented without using multipliers?

3. Calculate the required FPGA clock frequency when the FIR filter has following specifications? ADC clock frequency is 15 MHz, single channel FIR and number of coefficients are 56 and single MAC structure is used to realize the filter. Is the required FPGA clock frequency is practical with current FPGA devices? If not, how to change the filter structure to make it practical?

4. In the decimator block of Fig. 1, the sample rate is reduced by 4. After decimator, what will be new Nyquist frequency?

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