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Homework answers / question archive / Final ASSIGNMINT, ECE504 – Digital System Design Q1

Final ASSIGNMINT, ECE504 – Digital System Design Q1

Electrical Engineering

Final ASSIGNMINT, ECE504 – Digital System Design

Q1. (40 points) Design a digital alarm clock that has the following ports:

Inputs: 

CLK_1_SEC, RST, LOAD_TIME, SET_HOURS, SET_MINS, SET_SECS, SET_AM_PM, LOAD_ALM, ALARM_HOURS, ALARMS_MINS, ALARMS_AM_PM, ALARM_ENABLE, ALARM_DURATION

 

Outputs: 

HOURS, MINS, SECS, AM_PM, FLASHING, ALARM

 

The required characteristics of the digital alarm clock are:

  • timing it to be controlled from a 1 second input clock, CLK_1_SEC
  • to operate on 12-hour basis with separate AM/PM control
  • the value of time to be set when LOAD_TIME is high
  • the alarm time to be set when LOAD_ALM is high 
  • the ALARM output should go high when the current value of time is equal to the alarm time. The alarm should stay on until the ALARM_ENABLE signal goes low, which equates to turning the alarm off or after ALARM_DURATION minutes has elapsed when left on or RST/LOAD_ALM signal is set high. Note ALARM_DURATION can be lower than or equal to 10 minutes.
  • If power is lost and then powered up again, it should stay the time 00:00:00 and the “Flashing” signal should be activated high. This causes the display to flash and so indicate that the alarm clock’s time needs to be set. The flashing signal should stay high and the clock’s time should increase from zero until a new time is set. 
  1. (10 points) Draw the Moore machine state diagram with minimal states for the digital alarm clock system (both of time set and alarm set).  
  2. (20 points) Write a Verilog or VHDL module (with correct syntax) called digital_alarm for

 the given circuit in the behavioral design style. The module should be sensitive to rising edge of CLK input. (USE VIVADO PROGRAM TO WRITE VERILOG OR VHDL MODULE)

                                     

  1. (10 points) Write a Verilog or VHDL test bench  (with correct syntax) called  tb_digital_alarm  for the given circuit. Create a 1Hz CLK_1_SEC signal and apply the following input sequence:

 ALARM_HOURS = 4, ALARMS_MINS = 22, ALARMS_AM_PM = ‘0’,  ALARM_DURATION = 10, SET_HOURS = 1, SET_MINS = 7, SET_SECS = 9,  SET_AM_PM = ‘0’. Also set the rest of control input signals.  

 Run behavioral simulation and  attach the signal waveforms for inputs and output signals for the  given test.

                                                               (USE VIVADO PROGRAM TO WRITE VERILOG OR VHDL MODULE)

Q2. (20 points) A generic sequential circuit is given below. The circuit’s inputs are A, CLK and CLR and output is Y. The propagation delay of flip-flops (tCLK-Q) is 50ps, tsetup and thold time requirements are 50ps and 25ps respectively. Clock signal (CLK) has the clock skew value of 10ps.  (ps = picosecond, 10-12 second, GHz = Gigahertz, 109 Hertz)

 

D

Q

Q

CLR

D

Q

Q

CLR

Clock Skew

CLK

CLR

A

 

 

  1. (5 points) Assume that the delay of each combinational logic gate is calculated as d = number of inputsx50ps.Calculate the propagation delay for the combinational part of the circuit given in figure. Find the critical (largest delay) path for combinational part of the given circuit.
  2. (5 points) Calculate the minimum cycle time and the maximum frequency at which the circuit can operate.
  3. (5 points) Calculate the setup time slack when the circuit operates at 3.0GHz frequency. In order to have +50ps setup time slack, what should be the operating frequency of circuit?  D.            (5 points) Calculate the hold time slack when the circuit operates at 3.0GHz frequency. 

 

Q3. (25-points) The structure of a 32-bit carry-look ahead adder is shown in figure below. The inputs are 32-bits wide A and B signals. Cin is the input carry signal. From the adder, 32-bits wide S signal and 1-bit Cout signal is generated to produce 33-bits output signal. The add operation result is given at the rising edge of CLK signal. CLR is an active high clear signal to reset the output signal to logic 0. 

 

 

 

    1. (15 points) Write a Verilog or VHDL module (with correct syntax) called

           carry_look_32_bit for the given circuit in the behavioral design style

(USE VIVADO PROGRAM                                TO WRITE VERILOG OR VHDL MODULE)

    1. (10 points) Write a Verilog or VHDL test bench (with correct syntax) called

       tb_carry_adder for the given circuit. Create a 100MHz CLK signal and apply the

following input sequence:

                              Input Signals (A, B, Cin) = (32,56,1), (50,75,0), (5,64,0)  

 Run behavioral simulation and attach the signal waveforms for inputs and output signals  for the given test. The inputs are applied at the rising edge of CLK

 (USE VIVADO PROGRAM TO WRITE VERILOG OR VHDL MODULE)

     

    Q4 (15 points) A typical digital signal processing (DSP) system is given in figure below. ADC has

100MHz sampling clock and every samples will be captured by FPGA for backend processing.

An interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n). Then, a decimation block will reduce the sampling rate by a factor of 15 to generate sample  stream of z(n).

 

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FP

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LPF2

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z

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LPF1

 

 

 

A. (15 points) When LPF1 (Low Pass Filter 1) and LPF2 are implemented using a 30-taps FIR structure, and the system must operate in streaming way (every samples must be processed without any halt), what will be required FPGA clock frequency and what type of FIR filter structures should be used? Input samples are 12-bits and coefficients are 10-bits for both filters. Determine the number and the size of multiplication and addition operations in FPGA to implement LPF1 and LPF2. Comment on the bit growth and what kind of digital operations should be implemented before LPF2 to reduce the hardware cost?

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