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Homework answers / question archive / Final ASSIGNMINT, ECE504 – Digital System Design Q1
Final ASSIGNMINT, ECE504 – Digital System Design
Q1. (40 points) Design a digital alarm clock that has the following ports:
Inputs:
CLK_1_SEC, RST, LOAD_TIME, SET_HOURS, SET_MINS, SET_SECS, SET_AM_PM, LOAD_ALM, ALARM_HOURS, ALARMS_MINS, ALARMS_AM_PM, ALARM_ENABLE, ALARM_DURATION
Outputs:
HOURS, MINS, SECS, AM_PM, FLASHING, ALARM
The required characteristics of the digital alarm clock are:
the given circuit in the behavioral design style. The module should be sensitive to rising edge of CLK input. (USE VIVADO PROGRAM TO WRITE VERILOG OR VHDL MODULE)
ALARM_HOURS = 4, ALARMS_MINS = 22, ALARMS_AM_PM = ‘0’, ALARM_DURATION = 10, SET_HOURS = 1, SET_MINS = 7, SET_SECS = 9, SET_AM_PM = ‘0’. Also set the rest of control input signals.
Run behavioral simulation and attach the signal waveforms for inputs and output signals for the given test.
Q2. (20 points) A generic sequential circuit is given below. The circuit’s inputs are A, CLK and CLR and output is Y. The propagation delay of flip-flops (tCLK-Q) is 50ps, tsetup and thold time requirements are 50ps and 25ps respectively. Clock signal (CLK) has the clock skew value of 10ps. (ps = picosecond, 10-12 second, GHz = Gigahertz, 109 Hertz)
D |
Q |
Q |
CLR |
D |
Q |
Q |
CLR |
Clock Skew |
CLK |
CLR |
A |
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Q3. (25-points) The structure of a 32-bit carry-look ahead adder is shown in figure below. The inputs are 32-bits wide A and B signals. Cin is the input carry signal. From the adder, 32-bits wide S signal and 1-bit Cout signal is generated to produce 33-bits output signal. The add operation result is given at the rising edge of CLK signal. CLR is an active high clear signal to reset the output signal to logic 0.
carry_look_32_bit for the given circuit in the behavioral design style
(USE VIVADO PROGRAM TO WRITE VERILOG OR VHDL MODULE)
tb_carry_adder for the given circuit. Create a 100MHz CLK signal and apply the
following input sequence:
Input Signals (A, B, Cin) = (32,56,1), (50,75,0), (5,64,0)
Run behavioral simulation and attach the signal waveforms for inputs and output signals for the given test. The inputs are applied at the rising edge of CLK
Q4 (15 points) A typical digital signal processing (DSP) system is given in figure below. ADC has
100MHz sampling clock and every samples will be captured by FPGA for backend processing.
An interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n). Then, a decimation block will reduce the sampling rate by a factor of 15 to generate sample stream of z(n).
AD |
C |
x |
( |
t |
) |
FP |
G |
A |
LPF2 |
D |
ec |
im |
a |
t |
o |
r |
x |
( |
n |
) |
y( |
n |
) |
1 |
00 |
MHz |
z |
( |
n |
) |
In |
t |
e |
r |
p |
o |
l |
a |
t |
o |
r |
LPF1 |
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A. (15 points) When LPF1 (Low Pass Filter 1) and LPF2 are implemented using a 30-taps FIR structure, and the system must operate in streaming way (every samples must be processed without any halt), what will be required FPGA clock frequency and what type of FIR filter structures should be used? Input samples are 12-bits and coefficients are 10-bits for both filters. Determine the number and the size of multiplication and addition operations in FPGA to implement LPF1 and LPF2. Comment on the bit growth and what kind of digital operations should be implemented before LPF2 to reduce the hardware cost?