ECE 429 Final Exam (Take-Home)

Question 1) Let’s say we have a 0.22 μm (micrometer) think Cu wire in a 65 nanometer process. Resistivity of the Cu is 2.2 μ?? cm (micro-ohm?centimeter).

1. Compute the sheet resistance of the wire

2. Find the total resistance if the wire is 0.125 μm wide and 1mm long. (Ignore the barrier layer and dishing)

3. Suppose that 10x unit-sized inverter drives a 2x inverter at the end of the 1 mm long of the wire. Its wire capacitance is 0.2 fF/ μm and the unit-sized nMOS transistor has R=10k? and C=0.1 fF.  Complete the following equivalent circuit using a single-segment Π model.

4. Estimate the propagation delay using a single-segment Π Elmore delay model. (neglect diffusion capacitance)

                    2.                  

These questions are multiple choice questions that ask you to select only one answer choice from a list of three choices about temperature aware design in CMOSFET.

2.1) When temperature of a deeply scaled CMOS circuit is increased, then

1. the carrier mobility of the CMOS device will be

                      a) increased                     b) decreased         c) not changed 

2. the threshold voltage of the CMOS circuit will be

                 a) increased              b) decreased                c) not changed 

3. the sub-threshold leakage current of the CMOS circuit will be

                 a) increased              b) decreased                c) not changed 

4. the depletion region of the CMOS device will be

                 a) increased              b) decreased                c) not changed 

5. the junction capacitance of the CMOS circuit will be

                 a) increased              b) decreased                c) not changed 

6. the junction leakage current of the CMOS circuit will be

                 a) increased              b) decreased                c) not changed 

7. the active mode current (on-current) of the CMOS circuit will be

                 a) increased              b) decreased                c) not changed 

8. the standby mode current (off-current) of the CMOS circuit will be

                 a) increased              b) decreased                c) not changed 

2.2) Following table shows critical design corners that designers should consider one of the process corners when they compensate PVT variations and close design timing and power for CMOS IC design. Choose (make a circle) one of the corners in the table in order to guarantee a chip design specification.

3.

Provide a truth table that describes the functionality of each circuit in the Figure. (note: the output of the circuit may be high-Z) The symbol A’ refers to the complement of A.

 (a)

(b)

                    4.       Points)

Design a domino circuit whose output is

1. Out = + +AB            BC          C
2. Out = + + +(A         B          C) AB

5. (10 Points)

[ *Note: cd: Contamination Delay, s: Setup, h: Hold time, pd: Propagation delay ]

1. Find maximum clock frequency of the above sequential circuit

2. Is the circuit guaranteed to work correctly without any timing violations? Explain how you can say that?