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1 CPEG 312 – Final Exam - Spring2021 Problem #1 : a) (5 points) Show the binary code for storing the number 4

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1 CPEG 312 – Final Exam - Spring2021 Problem #1 : a) (5 points) Show the binary code for storing the number 4.75 in a floating point register according to IEEE format. b) (15 points) Suppose the following pipeline is designed for the integer and the floating point parts of the DLX processor. EX is integer ALU operation. A1, A2 represent floating point Add/Subtract and are internally pipelined. M1, M2, M3 represent floating point multiply and also is internally pipelined. IF ID MEM EX A1 A2 M1 M2 WB M3 DIV (4 cycles, not pipelined) For the following parts, show the number of clock cycles needed to execute the code, forwarding and feedback requirements, and stall detection logic. 1) ADDF F6, F3, F2 SUBF F2, F8, F7 DIVF F8, F2, F8 2) DIVF F8, F3, F4 ADDF F6, F3, F8 MULF F9, F4, F6 3) DIVF F8, F3, F2 DIVF F9, F3, F8 ADDF F7, F7, F8 1 2 Problem #2: a) (10 points) If a CPU has 24 address lines and 24 bit data bus. Show the design of fully associative L1 cache with 210 bytes of data memory. b) (10 points) If a CPU has 24 address lines and 24 bit data bus. Show the design of L2 (two way set associative cache) with 212 bytes of data memory. 2 3 c) (10 points) If a CPU has 24 address lines and 24 bit data bus. Show the design of L3 (direct mapped cache) with 214 bytes of data memory. 3 4 d) (15 points) If a CPU has 24 address lines and 24 bit data bus. Show the design of virtual memory (page lookup table) with page size of 512 bytes and a RAM with 216 bytes. Assume the page lookup table is implemented as fully associative memory. How an address from CPU will be translated to a physical address in RAM? 4 5 e) (10 points) Briefly Explain the difference between “Least Recently Used” and “Least Frequently Used” page replacement algorithm. Which one of these you will select to implement the page replacement policy in Virtual memory and why? 5 1 CPE 312 – Assignment #7 Problem #1 : a) (5 points) Show the binary code for storing the number 3.625 in a floating point register according to IEEE format. 0 1000 0000 110100……0 b) (15 points) Suppose the following pipeline is designed for the integer and the floating point parts of the DLX processor. EX is integer ALU operation. A1, A2 represent floating point Add/Subtract and are internally pipelined. M1, M2, M3 represent floating point multiply and also is internally pipelined. IF ID MEM EX A1 A2 M1 M2 WB M3 DIV (3 cycles, not pipelined) (following solution is by Jayne Sabovik) 1 2 Problem #2: a) (10 points) If a CPU has 22 address lines and 16 bit data bus. Show the design of fully associative L1 cache with 210 bytes of data memory. b) (10 points) If a CPU has 22 address lines and 16 bit data bus. Show the design of L2 (two way set associative cache) with 212 bytes of data memory. 2 3 c) (10 points) If a CPU has 22 address lines and 16 bit data bus. Show the design of L3 (direct mapped cache) with 214 bytes of data memory. 3 4 d) (15 points) If a CPU has 22 address lines and 16 bit data bus. Show the design of virtual memory (page lookup table) with page size of 256 bytes and a RAM with 216 bytes. Assume the page lookup table is implemented as fully associative memory. What page replacement algorithm will you use. How an address from CPU will be translated to a physical address in RAM?