Homework answers / question archive / CDA 4213 001/CIS 6930 012 CMOS VLSI Design Fall 2021 Lab 2 Assigned: Wednesday, 9th September 2021 Due 11:59 PM, Sunday, 19th September 2021 Note: This assignment carries 5% of the final grade

CDA 4213 001/CIS 6930 012 CMOS VLSI Design Fall 2021 Lab 2 Assigned: Wednesday, 9th September 2021 Due 11:59 PM, Sunday, 19th September 2021 Note: This assignment carries 5% of the final grade

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CDA 4213 001/CIS 6930 012 CMOS VLSI Design Fall 2021 Lab 2 Assigned: Wednesday, 9th September 2021 Due 11:59 PM, Sunday, 19th September 2021 Note: This assignment carries 5% of the final grade. No late work will be accepted. Start early! You must work individually on this assignment. No teaming for this assignment. Objective You will model and simulate some basic building blocks with Virtuoso and verify their functionality. Details For all of the following problems, assume a capacitive load of 0.1pF. 1. (5 pts.) NMOS Transistor Demonstrate that nMOS transistor is a good conductor of 0’s and poor conductor of 1’s. 2. (5 pts.) PMOS Transistor Demonstrate that pMOS transistor is a good conductor of 1’s and poor conductor of 0’s. 3. (10 pts.) Transmission Gate Model a transmission gate and demonstrate its functionality. 4. (10 pts.) 2-input Multiplexer Using the above transmission gate, build a 2-input multiplexer and verify its functionality. Deliverables (must be uploaded to Canvas course webpage by the deadline) • Lab report using the template provided. PDF only. • A compressed zip file (.tar.gz file) containing all your schematic diagrams as well as the simulated output. On Linux you can create a compressed archive of a folder as follows: prompt% tar czvf .tar.gz For example, executing the following command will compress the inv folder. prompt% tar czvf inv.tar.gz inv Tips 1. 2. 3. 4. Format your code well (just like you do in your C programs). Do not discard your files. We will use them in later assignments. A Word template will be provided which should be used for your report. Include all schematic diagrams, simulation waveforms. For simulation results, zoom in/out appropriately so that we can clearly see the input stimuli and the output response. Good Luck! CDA 4213 001L/CIS 6930 012 Fall 2021 CMOS VLSI Design Lab 2 Report Canvas Submission Due: 11:59 PM, 19th Sept. 2021 Note: Upload PDF version of this report. Only PDF format is accepted. Today’s Date: Your Name: Your U Number: No. of Hours Spent: Exercise Difficulty: (Easy, Average, Hard) Any Other Feedback: 1 Question 1 (5 pts): NMOS Transistor Include the following a) Transistor level diagram b) Screenshot of schematic c) Waveform results d) Explain how you demonstrate that NMOS transistor is good (poor) conductor of 0 (1). 2 Question 2 (5 pts): PMOS Transistor Include the following a) Transistor level diagram b) Screenshot of schematic c) Waveform results d) Explain how you demonstrate that PMOS transistor is good (poor) conductor of 1 (0). 3 Question 3 (10 pts): Transmission Gate Include the following a) Transistor level diagram b) Screenshot of schematic c) Waveform results 4 Question 4 (10 pts): 2-input Multiplexor Include the following a) Transistor level diagram b) Screenshot of schematic c) Waveform results 5