Q1) Consider the following floating-point format to perform the operations listed below S 4-bit excess exponent (E) 8-bit unsigned mantissa (M)   F = (-1)S x 1

Q1) Consider the following floating-point format to perform the operations listed below

F = (-1)^S x 1.M x 2^(E-8)

                                          Q1/A           Determine the number represented by the following bits given in the above          floating-point format      

 Q1/B  Determine the largest and the smallest (magnitude only) representable numbers in this  floating point format. Give your answers in decimal representation.

 Q2 . Truncation and rounding are widely used methods to reduce the bit length of            a digitaldata. Reduce the bit length of following unsigned binary number.

Number =  011.0011000011110

 Q2/A Truncate Number to 7 binary position. Find the error caused by the truncation^th operation  . in decimal representation. You can leave the result as power of 2.

            Q2/B    Symmetrically   round Number   to 7      binary position. Find the        ^th          error caused bythe

            .           rounding operation in decimal representation. You can leave the result as power of 2.     

 Q3 The  concept  of parity is widely used in digital systems for error-checking purposes.When  digital information is transmitted from one point to another, perhaps by long wires, it is  possible for some bits to become corrupted during the transmission process. A simple error checking mechanism can be implemented by including an extra bit, p, which indicates the parity of  the n-bit item. Two kinds of parity can be used. For even parity the p bit is given the value such that  the total number of 1s in the n + 1 transmitted bits (comprising the n-bit data and the parity bit p) is  even. For odd parity the p bit is given the value that makes the total number of 1s odd.

 Let’s design a three-bit parity generator. For every three bits that are observed on the input w  during three consecutive clock cycles, the FSM generates the parity bit p = 1 if and only if the  number of 1s in the three-bit sequence is odd and otherwise it generates the parity bit p = 0.

            Q3/A ) Draw the Moore machine state diagram with minimal    states.             

            Q3/B ) Derive a minimal state table for the given FSM.

            Q3/C) Drive minimized Boolean equations for the next state variables. Draw the circuit

  schematic for the LSB position  of state variables update logic using inverters, 2-input ANDs  and ORs.

 Q3/D) Write a Verilog or VHDL module (with correct syntax) called ParityGeneratorSM   for the given state machine in the behavioral design style. An asynchronous active high CLR  input signal is used to reset the state  machine to initial state position. The module should be sensitive to rising edge of CLK input.

            Q3/E)   Write a Verilog or VHDL test bench      (with correct syntax) called                            tb_parity         for the

  given state machine. Create a 100 MHz CLK signal and apply the following input sequence:  w = 010100110111011010   

 Run behavioral simulation and attach the signal waveforms   for states, inputs and output signals for the given test.  

            Q4        A  typical digital signal processing (DSP) system is given in figure below. ADC has

 100 MHz sampling clock and every samples will be captured by FPGA for backend processing. An  interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n). Then, a decimation block will reduce the sampling rate by a factor of 15 to generate sample stream of z(n).

 Q4/A Calculate the signal bandwidths  (Nyquist bandwidth ) for sample streams of  x(n), y(n)  and z(n). Find the ratio between the sampling rate of z(n) to x(n). 

NOTE:       I want to make a clarification about the Q2 . After truncation/rounding you will get a binary number with 10-bit length including integer and fractional part.

NOTE ; use vivado program to write veriloqe or VHDL