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Module Learning Outcomes The following LOs are achieved by the student by completing the assignment successfully 1. Explain MOSFET construction, operation and pass characteristics; 2. Analyse high performance Dynamic CMOS circuits; 3. Explain the basic processing steps for fabricating the integrated circuits; Assignment Objective The objective of the assignment is to ensure the achievement of the learning process related to MOSFET operation, fabrication and concepts of dynamic CMOS circuits. Assignment Tasks
1. Consider a MOSFET built on p-type substrate having the following parameters VT0=1V, |2ΦF|=0.54V, process trans-conductance=45 µA/V2 , γ=0.17V1/2 , λ=0.04V-1 a. Find the type of MOSFET. b. Determine the threshold voltage(VT) and W/L, When the transistor is biased with VG=4V, VD=4V, VS=2V, and VB=0V and the drain current ID=0.87mA c. Calculate ID for VG=5V, VD=3V, VS=2.2V, and VB=0V. 2. a. Explain the processing steps for patterning a polysilicon layer as shown in Figure 1(a) to the structure as shown in Figure 1(b) with neat sketches.
b. Dynamic logic is considered to be temporary storage compared to static logic; justify the statement. c. For the given domino logic circuit in Figure 1, during evaluation , if A=1, B=1, C=1 and D=0 will cause charge sharing and the input to the inverter will drop. The minimum voltage required at the inverter input is 2.5V. What should be the maximum CP/CL ratio to avoid charge sharing affect the correct output at F?
3. a. Realize the given expression using ???????????????? = ????(???? + ????)???? + ???? i. Psuedo NMOS logic ; ii. Dynamic Domino Logic b. Realize the following function using NORA CMOS Logic. ???? = ((???? + ????) ??????????. (???? + ????) ?????????????????????? . ???? + ????) ????????????????????????????????? 4. a. Compare different logic families with reference to noise margin, fan-in, and power dissipation and suggest suitable field of application. Include RTL, ECL and NMOS logic family in your comparison. b. Compare an enhancement mode and depletion Mode MOS transistors in terms of threshold voltage and operating conditions.
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