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Instruction cycles are concerned with the fetch and execute cycle

Computer Science

Instruction cycles are concerned with the fetch and execute cycle." Justify the answer with necessary block diagram (10 Marks)

"A program alone cannot perform all the tasks. It needs some additional routines." Explain the statement (10 Marks)

Learning Outcome: Describe the design of arithmetic and logic unit in a computer system. (Total: 20 marks)

QUESTION 2

a) Micro instruction sequencing is better than hardwired instruction sequencing. Identify some situations when hardwired instruction sequencing is preferred. (12 Marks)

b). Represent the following twos complement values in decimal:

i) 1101011 (3 Marks)

ii) 0101101. (3Marks)

Explain addition and subtraction operations with signed 2's complement integer data. (6 Marks)

Learning Outcome: Demonstrate the basic understanding in hardware control and binary arithmetic operations. (Total: 24 Marks)

QUESTION 3

a) Assume a pipeline with four stages: fetch instruction (FI), decode instruction and calculate addresses (DA), fetch operand (FO), and execute (EX). Draw a diagram for a sequence of 7 instructions, in which the third instruction is a branch that is taken and in which there are no data dependencies. (10 Marks)

b). A conditional branch instruction makes the address of the next instruction to be fetched unknown. Thus, the fetch stage must wait until it receives the next instruction address from the execute stage. The execute stage may then have to wait while the next instruction is fetched.

Briefly explain various ways in which an instruction pipeline can deal with conditional branch instructions (6 Marks)

Learning Outcome: Analyze pipelined control units in a computer system (Total: 16 Marks) QUESTION 4

a)List and define the fields of the main memory address in the direct-mapped cache, associative cache and set-associative cache i)For a direct-mapped cache, a main memory address is viewed as consisting of three fields. List and define the three fields. The fields would be i, j, and m. I is the cache line number, j is the main memory block number, and m is the number of lines in the cache. (Marks 3)

ii) For an associative cache, a main memory address is viewed as consisting of two fields. List and define the two fields. Tag and Word fields. Tag field uniquely identifies a block of main memory. The word is what is to be placed in the block of memory. (Marks 3)

iii) For a set-associative cache, a main memory address is viewed as consisting of three fields. List and define the two fields. The fields are Tag, Set and Word. The tag identifies a block of main memory, the set specifies one of the 2^s blocks of main memory. The word is what is to be placed in the main memory. (Marks 2)

b) "An interrupt I/O is a process of data transfer through which an external device or a peripheral informs the CPU that it is ready for communication and requests the attention of the CPU."

Elaborate the answer with suitable example and block diagram (12 Marks)

c) An I/O-bound program is one that, if run alone, would spend more time waiting for I/O than using the processor. A processor-bound program is the opposite. Suppose a short-term scheduling algorithm favors those programs that have used little processor time in the recent past. Explain why this algorithm favors I/O-bound programs and yet does not permanently deny processor time to processor-bound programs (12 Marks)

Learning Outcome: Evaluate the performance of memory systems & Input and output organization (Total: 32 Marks)

QUESTION 5

a) "Use of multiprocessor systems in real-time applications is becoming popular". Justify your answer with suitable example. (8 Marks)

Learning Outcome: Explain the parallel processing architectures in computer technologies.

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