Homework answers / question archive / Q1 (20 pts): Assume program execution time consists of 60% CPU time and 40% memory time that do not overlap

Q1 (20 pts): Assume program execution time consists of 60% CPU time and 40% memory time that do not overlap

Computer Science

Share With

Q1 (20 pts): Assume program execution time consists of 60% CPU time and 40%
memory time that do not overlap. Which is a better enhancement for the overall
performance and why?
(a) Improve the CPU speed by 100%
(b) Reducing the memory access time by 4 times
Q2 (80 pts): Goal: Understand the performance of the single-cycle processor, the multicycle processor, and the processor with the instruction pipeline through functional
simulation.
Description of the Assignment: While earlier processors used single-cycle and multicycle data path designs without pipelining, instruction pipelines have become essential
for improving performance for a variety of processors. In this assignment, you will write
a simulation of a sequence of “instructions” moving through a CPU data path. This
simulation takes three forms as discussed in the class: 1) a single-cycle implementation,
where each instruction takes exactly one clock cycle to execute (but this clock cycle must
be long enough to handle all of the requirements of the longest instruction type); 2) a
multi-cycle implementation, where each instruction can take multiple clock cycles but
cannot overlap the execution with other instructions; and 3) a pipelined implementation,
where multiple instructions can simultaneously be in different partial stages of execution.
Note that you are not asked to simulate the detailed execution of the instruction, for
example, fetching, decoding, executing, memory, and writing back, nor to analyze the
data and control dependence and identify pipeline hazards at runtime. To simplify the
simulation, the actual instructions are not identified – in other words, there is no
instruction type, and every instruction takes the same amount of time on the same data
path but of course differs on different data paths. We also assume that each instruction is
independent of the other instructions; thus, there is no pipeline hazards.
The pseudo-code of simulating three different data paths is provided below.
Pseudocode of Single-Cycle Program
Data:
cycles // Keeps track of total clock cycles used
i // Instruction counter
Procedures:
main()
{
cycles = 0
for (i = 1 to the number of instructions)
{
cycles = cycles + 1
2
output current state
}
output results (cycles * cycle length)
}
Pseudocode of Multi-Cycle Program
Data:
instructions[] // Initialized to the number of cycles required by each instruction.
cycles // Keeps track of total clock cycles used
i // Instruction counter
Procedures:
main()
{
cycles = 0
for (i = 1 to the number of instructions)
{
for (j = 1 to instructions[i])
{
cycles = cycles + 1
output current state
}
}
output results (cycles * cycle length)
}
Pseudocode of Pipelined Program
Data:
cycles // Keeps track of total clock cycles used
i // Instruction counter
pipeline[] // Keeps track of which instruction is in which stage of the pipeline
Procedures:
main()
{
cycles = 0
i = 0
while (an unfinished instruction exists)
{
cycles = cycles + 1
// advance all instructions in pipeline
for (j = pipeline length down to 1)
pipeline[j] = pipeline[j-1]
pipeline[0] = i
i++
output current state
3
}
output results (cycles * cycle length)
}
Submission: you need to submit to Blackboard with the following documents:
The source code of three different “simulators”.
The executable code of three different simulators.
The test inputs (i.e., code sequence) you used to evaluate the performance on different
data paths.
A report to summarize the simulation and performance evaluation of the three different
data paths. In your report, you also need to describe the format of the input data and
the command line arguments to run the simulator for each data path, since the TA may
generate or use different testing inputs other than what you provide.
Note that this is not a team assignment. You need to work on your own and submit your
own work.