Homework answers / question archive / Assignment – Digital Electronics - 2021-2022 Total marks: 50 (Each question carries equal marks) The block diagram shown in Figure Q1 illustrates the steps involved in displaying a decimal number using a seven segment LED display

Assignment – Digital Electronics - 2021-2022 Total marks: 50 (Each question carries equal marks) The block diagram shown in Figure Q1 illustrates the steps involved in displaying a decimal number using a seven segment LED display

Electrical Engineering

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Assignment – Digital Electronics - 2021-2022 Total marks: 50 (Each question carries equal marks)

1. The block diagram shown in Figure Q1 illustrates the steps involved in displaying a decimal number using a seven segment LED display. This has three modules, namely decimal to BCD (D2BCD) converter, BCD to 7 (BCDto7) -segment decoder and 7-segment display. The D2BDCD has 10 inputs and 4 outputs. By switching ON any one of the inputs of D2BCD, the Vdd will be applied to the corresponding input indicating the respective decimal number is selected. Following which the D2BCD will generate appropriate BCD output. Next the BCDto7 decoder (has 4 inputs and 7 outputs), converts the BCD numbers to the respective logic for the 7-segment display. The output of the BCDto7 segment decoder drives common anode type 7-segment display.

Design a logic circuit with optimized number of logic gates by employing the K-map minimization technique to display ONLY any one of the last two digits of your student ID. (For an example if ABCDxx is the student id, then xx represents the last two digits). For any other digits other than the last two digits, the circuit should display 0. [Note: if the last two digits of your ID are same, then replace one number that is greater or smaller than the current number. Similarly, any one or both numbers in the last two digits are 0 then chose two non-identical numbers to replace 0s]

[10 marks for the D2BCD design+ 15 marks for the BCDto7segment decoder]

Figure Q1

2. The flip-flop circuit in Figure 2(a) is used to generate a binary count sequence. The gates form a decoder that is supposed to produce a HIGH when a binary zero or a binary three state occurs (00 or 11). However, when checking QA and QB outputs (as shown in Figure 2(b)) glitches on the decoder output (X) are detected in addition to the correct pulses. Explain the cause for the occurrence of the glitches and provide possible circuit to eliminate them?

Figure 2(a)                                                                          Figure 2(b)

[15 marks for the correct answer for the glitch and 10 marks for glitch elimination circuit]

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