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HW NO 3, ECE531 - Advanced Electronic Design Techniques (40 points) The following sequential circuit is given to a designer

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HW NO 3, ECE531 - Advanced Electronic Design Techniques

1. (40 points) The following sequential circuit is given to a designer. Positive edge triggered D flip-flops are used to store input and output data. Input capacitance of D flip-flops are equal to 64*input cap. of the template inverter. t_setup, t_hold and t_CLK-Q timing parameters for the flipflops are 100ps, 150ps and 50ps respectively. Use τ = 7.3ps and assume an ideal CLK design.
   1. (10 points) Let’s size all gates (C₂, C₃, …., C₉) that have the same input capacitance of the template inverter. Estimate delay using Logical Effort method? Show the critical path. Find the maximum frequency of CLK at which the given circuit can operate. Check the hold time requirement for all flip-flops.
   2. (15 points) Let’s size all gates (C₂, C₃, …., C₉) for minimum delay. Estimate delay using Logical Effort method? Show the critical path. Find the maximum frequency of CLK at which the given circuit can operate. Check the hold time requirement for all flip-flops. 
   3. (15 points) When the designer is allowed to add inverters for delay optimization, how many inverter stages should be added to each path for the given circuit. After addition of inverters, estimate delay using Logical Effort method? Show the critical path. Size all gates using new number of stages and draw the new circuit schematic. Calculate the sum of input capacitances of all gates (C₁, C₂, …., C₉ and additional inverters excluding flip-flops) to estimate the energy consumption of the circuit. Calculate Energy*Delay values for initial design and inverter added design to calculate possible optimizations. Comment on the Energy, Delay and E*D product after addition of inverter stages. 

	Energy (Sum of cap.)	Delay (ps)	E*D (ps*sum_of_cap.)
Original design
Modified design
Reduction (%)

 

 

2. (30 points) Assume that a capacitor that has a value of C charged up to voltage level of Vdd. Initially, NMOS transistor is in off-state and an ideal input of Vin is applied to gate input of NMOS transistor. Transistor is turned on and the capacitor starts to discharge. The fall delay is defined as the time duration between the 50% of input signal (V_in) to the output signal (V_out). Drive fall delay of the following circuit. Assume that NMOS device will operate in saturation and linear regions while Vout goes from Vdd to Vdd/2. 

(Hint:?I_d ?^{C dVout}_dt                   => dt_{?? I}C dVout , use current equation formulas of MOS device and do d

math)

 

                                                    Vout                                                                                     Vdd

 

t

f

Vdd

/

2

Vdd

-

Vt

I

d

GND

C

V

in

VinVout

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3. (30 points) Instead of using calculated values of logical effort (g) and parasitic (p), more accurate delay estimation is possible by using a gate characterization setup to capture measured g and p values.   Use the gate characterization setup given below to measure the logical effort (g) and the parasitic (p) of INV and NAND2 gates. Use V_dd = 1.2V, p/n ratio is 2.0, W_min = 25nm, L_min = 25nm. Repeat the measurement starting rom h = 2 to h = 10. Plot the delay versus h and then use a curve fitting tool (Microsoft Excel or Matlab) to calculate τ, g_inv, p_inv, g_nand2, p_nand2. Use 22nm predictive technology model in the measurements. You can use any Spice based circuit simulator such as LTSPICE. Provide schematic of gates including sizes, gate characterization setup and an example of input/output waveform captured from the simulator. For multiple input gates, only one input characterization is sufficient, other inputs can be fixed to a constant input.

Hint: Process technology file, a LTSPICE demo and Excel based technology characterization file are added to Collab System.

You can increase the size of a gate by h times to create h copy of that gate. Use 0.1pF capacitors at the output of (h-1)*h and h*h copy of gates as a load. Connect bulk port of NMOS to GND and bulk port of PMOS to Vdd. 

In your simulation, use a pulse input with the following specifications and measure rise and fall delays for the gate under test.