Homework answers / question archive / Homework-1, ECE531 – Advanced Electronic Design Techniques (15 points) Size each transistor [(W/L)1, (W/L)2, …, (W/L)6] to have the same equal pull up and pull down resistance as the reference CMOS inverter

Homework-1, ECE531 – Advanced Electronic Design Techniques (15 points) Size each transistor [(W/L)1, (W/L)2, …, (W/L)6] to have the same equal pull up and pull down resistance as the reference CMOS inverter

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Homework-1, ECE531 – Advanced Electronic Design Techniques

1. (15 points) Size each transistor [(W/L)₁, (W/L)₂, …, (W/L)₆] to have the same equal pull up and pull down resistance as the reference CMOS inverter. Calculate the logical effort (g_up, g_down, g_avg) and parasitic (p_up, p_down, p_avg) for each input of the following gate. Find the Boolean function implemented by the gate, q = ?

                                                                                              Reference CMOS Inverter

2. (15 points) Calculate the logical effort (g_up, g_down, g_avg) and parasitic (p_up, p_down, p_avg) for each input of the following asymmetric gate.

3. (30 points) Skewed CMOS inverter gate have a p/n ratio different than 2.0. Calculate and plot the p/n ratio versus the rising and falling delay for the given path using logical effort theory. Find the p/n ratio of the inverter which gives the best delay for the following path. Find the minimum delay of the following path.

Cout = 256Cin

4. (40 points) Size the following circuit using LE and determine the total delay and size of each gate when Coff-path = 0, Coff-path = 5, Coff-path = 30 and Coff-path = 120.  
   1. Use the non-iterative solution method. Ignore the off-path capacitance and size the circuit using LE. Then, add the off-path capacitance to calculate the delays. Don’t change the initial sizing of each gate.  
   2. Use iterative solution. Iteratively size each gate (C₂, C₃ and C₄) to reduce the total delay. Start with C_off-path = 0 solution and iteratively solve for other cases. 
   3. Report the differences between iterative and non-iterative solution in terms of path delays. 

                   C₁ = 1                    C2                                         C₃                                           C4

Coff-path