Fill This Form To Receive Instant Help

Help in Homework
trustpilot ratings
google ratings


Homework answers / question archive / Homework-1, ECE531 – Advanced Electronic Design Techniques Q1

Homework-1, ECE531 – Advanced Electronic Design Techniques Q1

Electrical Engineering

Homework-1, ECE531 – Advanced Electronic Design Techniques

Q1. ) Derive p/n transistor ratio that delivers the best speed. Explain why it is different from 2.0 for 0.25µm CMOS process?  

              

Hint: Let’s use the circuit in figure-1 to derive p/n ratio for the best speed behavior. In the figure-1, an inverter derives another identical one and the p/n ratios for the both inverter is 1/1. The parasitic  capacitance from the drain of NMOS of driving inverter to GND can modeled as Cdn and similarly, for the PMOS, the parasitic capacitance from the drain to VDD is Cdp as seen in the figure-1. The gate capacitances of NMOS and PMOS of the second inverter can be modelled as Cgn and Cgp as seen in the figure-1. The equivalent resistances of the unit-width NMOS and PMOS are Reqn and Reqp respectively.      

 

In the Figure-2, PMOSs are sized by factor k and. Let’s ignore the wire capacitance for this derivation. For the 0.25µm CMOS process with L=Lmin, the equivalent resistances are 13k? and 31k? for NMOS and PMOS respectively [1]. 

 

[1]. Digital Integrated Circuits, Second Edition, Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic 

    

Q2.  Implement the equation x = [( ?a + b*)( ?c + d* + e?) + ?f)]g? using complementary CMOS. Size

the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 1 and PMOS W/L= 2 having equal pull-up and pulldown resistance. Suggest an implementation that will be fastest (in your view). Suggest the critical path of your implementation. Run LT-Spice Simulation and report the following delays. Use 22nm CMOS predictive model that is available in the system. Assume minimum sized NMOS and PMOS, (W/L) = (0.1u/0.1u). Set a, b and g to logic LOW. Set c, d and e to logic HIGH. Connect input f to a pulse voltage source with the following set of parameters. Measure and report the tphl and tplh delays with the corresponding waveforms. Also add the circuit schematic. Repeat the similar measurement for other combination of inputs to see the how the propagation delay is changing depending on the inputs to find the critical path.  

    

Q3.) Do a literature search, use the library, google etc about the leakage power (static power dissipation). Select and summarize a paper that is proposed to reduce the leakage power (static power dissipation).  

 

Option 1

Low Cost Option
Download this past answer in few clicks

26.99 USD

PURCHASE SOLUTION

Already member?


Option 2

Custom new solution created by our subject matter experts

GET A QUOTE