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Problem 1: Silver

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Problem 1: Silver. Your Rhodium Is Awful (38pts)

Welcome to the land of uncertainty. Explore these tragically True or frighteningly False statements. fill in the circle corresponding to the appropriate choice (True or False). For example, if any given statement is True, you should fill in the first circle, such that  becomes  . Otherwise, fill in the second circle False.

Warning: you must blacken the circle–x’s and check marks might not be graded correctly.

Zero points for a blank answer. Two points per correct action, and no partial credit. If you feel the need to write an explanation, don’t–it won’t be graded.

	Statement	True	False
(a)	In sequential computers, insructions are started and finish in compiler order.
(b)	The MIPS64 ISA can run on both sequential and pipelined architectures.
(c)	The MIPS64 ISA can support either a Little Endian or a Big Endian memory organization, depending on the compiler.
(d)	The instruction ADD.D F14, F0, F0 is a valid MIPS64 instruction to initialize F14 to zero. .
(e)	The maximum number of MIPS64 instructions is 64 because the number of unique opcodes that can be referenced with 6 bits is 26 ≡ 64
(f)	The MIPS64 instruction SH 124(R0), R6 will never produce a byte alignment error in byte addressable memory.
(g)	The MIPS64 instruction XORI R1, R0, # -1 will initialize R1 to 0xFFFF FFFF FFFF FFFF

	Statement	True	False
(h)	The 64-bit unsigned binary number with the largest magnitude has the same bit pattern as the 64 bit long twos complement representation of -1.
(i)	The MIPS64 instruction LB R3, 23(R9) will never result in a byte alignment error in byte addressable memory.
(j)	RISC architectures will typically support many register addressing modes.
(k)	The sign bit of a double precision floating point number in a byte-addressable Big Endian architecture is stored in the byte at address P, where P = 0 mod 8.
(l)	An ALU instruction for a load-store ISA typically has one operand in memory.
(m)	All MIPS64 branch instructions are j-type instructions.
(n)	The MIPS64 instruction L.D F16, 16(R0) uses the integer ALU portion of the CPU.
(o)	To avoid computing the effective address at run time, the MIPS64 ISA supports absolute addressing mode, where L.D F6, (1024) loads register F6 with the 8-bytes at address 1024.

 

 

 

	Statement	True	False
(p)	An instruction for a stack architecture has one operand on the stack and one in the instruction.
(q)	Subtracting one 2’s complement integer from another 2’s complement integer with the same sign will never overflow.
(r)	The MIPS64 instruction XOR R2, R3, R3 will initialize R2 to zero.
(s) ‘	The instruction S.D F4, 24(R0) will usually stall in the EX stage in the floating point pipe-like-pipe.

 

 

Problem 2: Extra Gallium? You Promised Titanium! (3pts) Get the reference sheet from piazza now!

You will need it for the remainder of the exam!

Note: This problem was denied entrance to the exam for refusing to be tested or vaccinated for covid19. However, you must include this page when scanning your exam or you will not receive the three points and may lose a few more if we can’t find your answers where they are supposed to be.

Problem 3: Gold, Helium And Neodymium Attract (56pts)

In this problem, you must answer questions regarding the code fragment below, assuming that it is run on a sequential implementation of a MIPS64 ISA using a byte addressable Big Endian memory organization. Further information regarding the MIPS64 ISA and the layout of the sequential machine can be found on the reference sheet supplied with the exam. Your job is to answer the questions that follow the MIPS64 code fragment below using only the commands listed on the SST 2 Resource Sheet posted on piazza.

For full credit, you must justify your answer and include any additional assumptions neededf to support your reasoning. Unless otherwise stated, each clearly labeled correct answer is worth 4 points.

				Ins Type
(1)		DADDI	R1, R0, #8
(2)		DADDI	R2, R0, #-8
(3)		DADDI	R5, R0, #7188
(4)	fiji:	LD	R16, -8(R1)
(5)		DADDI	R1, R1, #8
(6)		XOR	R3, R3, R3
(7)		LD	R24, 72(R2)
(8)		DSUB	R2, R0, R1
(9)		SD	-16 (R1), R24
(!0)		SD	80(R2), R16
(11)		DADD	R3, R2, R1
(12)		SD	1024(R5),R3
(13)		DADDI	R7, R1, #-72
(14)		BEQZ	R7, togo
(15)		J	fiji
(16)	togo:	SD	64(R5), R3

Please be sure to print or write your answer neatly in the area specified below the question to assist the automatic grading program.

3.1 (16) Put the appropriate MIPS instruction type in the “Ins Type” column provided for each instruction in the code fragment.

3.2 (4) How much memory do these sixteen (16) lines of MIPS64 code occupy? Justify your answer for full credit.

3.3 In instruction (7), LD R24, 72(R2), what is the memory address of the displacement value 72? For full credit, give the address and contents of both the MSB and the LSB associated with the immediate portion of the instruction

3.4 A misaligned memory access would be expected to cause this MIPS64 machine to crash at run time. Is this code fragment aligned correctly? If your answer is Yes, print Yes in the appropriate space below, and move on. If your answer is No, print No in the first space below. Print the instruction containing the misaligned memory reference in the 2nd space, being sure to identify where it occurs in the instruction.

                Neatly print YES or NO:                                     ]

             Neatly Explain Why:        

3.5 How is the label fiji on instruction (4) represented after this fragment is converted to machine code? Be as specific as possible. (Hint: what types of MIPS instructions do we have and what information do they contain.)

 

				Ins Type
(1)		DADDI	R1, R0, #8
(2)		DADDI	R2, R0, #-8
(3)		DADDI	R5, R0, #7188
(4)	fiji:	LD	R16, -8(R1)
(5)		DADDI	R1, R1, #8
(6)		XOR	R3, R3, R3
(7)		LD	R24, 72(R2)
(8)		DSUB	R2, R0, R1
(9)		SD	-16 (R1), R24
(!0)		SD	80(R2), R16
(11)		DADD	R3, R2, R1
(12)		SD	1024(R5),R3
(13)		DADDI	R7, R1, #-72
(14)		BEQZ	R7, togo
(15)		J	fiji
(16)	togo:	SD	64(R5), R3

 

 

3.6 What impact on the code fragment’s results, if any, would you expect to see if we replace instruction

(2) with instruction (2U) DADDIU R2, R0, # -8. Please be sure to explain your answer.

3.7 Assume that DSUB dest source1 source2 assigns (source1-source2) to dest. Suppose that we inserted a break-point right after instruction (12).

Since you have the values of all registers involved in the computations you should be able to give expressions for the contents of registers R3 and R5 after instruction (12). You should also be able to explain the impact of the previous instructions on memory.

3.8 True or False? The value written to memory by instruction (12) remains unchanged after each iteration of the loop. Explain your answer for full credit.

3.9 Identify two distinct instructions having the same immediate value. If none exists circle the word None.

Otherwise, write the numbers of the instruction and the shared constant.

3.10 Identify two distinct instructions where the destinations satisfy the same post conditions If none exists circle the word None. Otherwise, write the numbers of the instruction and the shared result.

3.11-3.14 If you like to evaluate code, please feel free to enjoy answering the next few questions.

Changes in either or both of the hardware and software for a given machine have the potential to change the execution time of a code fragment. Standard software-based techniques instruct the compiler to remove unnecessary or redunant instructions; move calculations of loop-independent parameters outside the loop; replacing if-then-else statements with conditional moves (called MOVZ and MOV on the MIPS64 handout), use multiplication instead of division, and convert switch statements into look-up-tables.

3.11 Your first job is to identify an instruction that could be moved outside of the loop without any impact on the contents of the registers and memory after the last instrucrion. There exists at least one. Identify it and speculate regarding the impact of this change on the execution time.

3.12 If possible, find another instruction, distinct from the first, and repeat the process in 3.11. If no such instruction is present, circle the term None.

3.13 After a brief analysis, you should be able to describe the purpose of the code using the state of the system when the code fragment terminates. We are looking for a few words here describing what, if anything has changed, not a comment for each instruction.

3.14 Aside from the code’s principal function, which you may or may not have discussed in 3.13, is there anything odd that about the code. Would you really expect it to get to instruction 16 successfully. Why or why not?

Problem 4: Platinum Erbium Refactored Uranium (64pts

Write MIPS64 code fragments that satisfy the following post conditions or “after execution” requirements, for 4 points each. Or, if no such fragment can be constructed, explain why. Assume that we are using a Big Endian version of MIPS64. You must use the instructions on the SST2 MIPS Resource to be found on piazza.

4.1 Write a MIPS64 code fragment with the post condition that register R1 contains the two’s complement representation of 810

4.2 Write a MIPS64 code fragment that will load R5 with the 8 byte word at a memory address that is 7188 bytes after the contents of register R1.

4.3 Write a MIPS64 code fragment that transfers control to an instruction labeled oolong when register R3 does not contain a zero.

4.4 Write a MIPS64 code fragment with the post condition that register F16 contains the 8 bytes of information at memory address 8192.

4.5 Write a MIPS64 code fragment with the post condition that register R7 contains the bit pattern below: 0x0000 0000 0000 FFF8

4.6 Write a MIPS64 code fragment that transfers a 4 byte word from memory address 0x5500 0055 to register R19.

4.7 Write a MIPS64 code fragment that swaps the contents of registers R9 and R29. A full credit answer will not use any load or store instructions. At most half credit for using them or any of the special “move” instructions. Please include any assumptions required to make your answer correct.

4.8 Write a MIPS64 code fragment that initializes register R26 to 2²⁶

4.9 Write a MIPS64 code fragment with the post condition that register R25 contains the double precision floating point number found in memory if the address of the Least Significant Byte of the number is in register R20.

4.10 Write a MIPS64 code fragment that will put the sum of the the first four odd numbers and the square root of 81 in R20.

4.11 Write a MIPS64 code fragment that initializes register R22 to four(4). At most half credit if you use any I-type instructions or any immediate operands. Be sure to include any assumptions required to make your answer correct.

4.12 Write a valid MIPS64 instruction with the post condition that register R2 contains the 2’s complement of the value in R20. At most half credit if your response is correct but requires more than one instruction.

4.13 Write a MIPS64 code fragment that initializes register R19 to 16²⁵₋ 16⁵. Explain your answer neatly and clearly to be eligible for partial credit.

4.14 Write a MIPS64 code fragment with the post condition that register F23 contains 1.732.

4.15 Write a MIPS64 code fragment that will reverse the order of the 8 bytes in the double word stored at address 2048. That is, the original MSB will be the address originally occupied by the original LSB and vice versa. The byte with the address next to the original MSB position will be moved to the address next to the original LSB position and so on. Partial credit for sketching the before and after postions of the 8 bytes.

4.16 Write a MIPS64 code fragment with the post condition that the memory location that is 64 bytes before R17 will contain the product of F2 and the 8 byte floating point number **fp where R5 contains the address of the pointer fp

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