Stevens Institute Of Technology

CS 550

Chapter 8: CPU and Memory Design Enhancement and Implementation

1)CPU architecture is defined by the basic characteristics and major features of the CPU. “CPU architecture” is sometimes called

1. 1. architecture design
   2. structural organization
   3. instruction set architecture
   4. CPU design and organization

 

2. The use of fixed-length, fixed-format instruction words with the op code and address fields in the same position for every instruction would allow instructions to be fetched and decoded
   1. independently.
   2. dependently and in parallel.
   3. independently and in serial.
   4. independently and in parallel.

 

3. There are several factors that determine the number of instructions that a computer can perform in a second. Which of the following is NOT a factor?
   1. Word size
   2. Clock speed
   3. Instruction format - fixed or variable
   4. Number of steps required by each instruction type

 

4. The                              must be designed to assure that each step of the instruction cycle has time to complete before the results are required by the next step.
   1. ALU
   2. clock cycle
   3. Control Unit
   4. instruction pointer

 

5. The fetch unit portion of the CPU consists of an instruction fetch unit and an instruction                                             

unit.

1. 1. decode
   2. translate
   3. decipher
   4. conversion

 

6. The                                 unit contains the arithmetic/logic unit and the portion of the control unit that identifies and controls the steps that comprise the execution part for each different instruction.
   1. fetch
   2. decode
   3. execution
   4. conversion

 

7. Overlapping instructions—so that more than one instruction is being worked on at a time—is known as the
   1. conveyor belt method.
   2. pipelining method.
   3. assembly line method.
   4. accelerator method.

 

8. Instruction reordering makes it possible to provide parallel pipelines, with duplicate CPU logic, so that multiple instructions can actually be executed
   1. sequentially.
   2. consecutively.
   3. simultaneously.
   4. very fast in serial operation.

 

9. Which of the following is not a specific execution unit?
   1. steering unit
   2. LOAD/STORE unit
   3. integer arithmetic unit
   4. floating point arithmetic unit

 

10. A(n)                                      processor is one that can complete an instruction with each clock tick.

a) linear

d) direct

3. scalar
4. express

 

11. There are a number of difficult technical issues that must be resolved to make it possible to execute multiple instructions simultaneously. One of the most important of these is

1. Instructions completing out of order.
2. Instructions that have floating point operations.
3. Instructions that can be serialized.
4. Instructions that require the same number of CPU cycles complete.

 

12. Out-of-order instruction execution can cause problems because a later instruction may depend on the results from an earlier instruction. This situation is known as a                                      or a                                          .

b) risk, reliance

a) hazard, reliance

d) risk, dependency

c) hazard, dependency

 

13. CPUs can actually search ahead for instructions without apparent dependencies, to keep the execution units busy. Current Intel x86 CPUs, can search                                       instructions ahead, if necessary, to find instructions available for execution.

1. five to ten
2. ten to twenty
3. twenty to thirty
4. fifty to one hundred

 

14. Branch instructions must always be processed ahead of subsequent instructions. Conditional branch instructions are more difficult than unconditional branches. These types of dependencies are known as control dependencies or sometimes as                                          or branch dependencies.

1. flow
2. decision
3. qualified
4. provisional

 

15. Some systems provide a small amount of dedicated memory built into the CPU that maintains a record of previous choices for each of several branch instructions that have been used in the program being executed to aid in determining whether a branch is likely to be taken. What are the contents of this memory called?

1. look-ahead table
2. branch history table
3. branch prediction table
4. future speculation table

 

16. What are the slowest steps in the instruction fetch-execute cycle?

1. Slowest steps are those that require memory access.
2. Slowest steps involve incrementing the instruction pointer.
3. Slowest steps are those that require special integer register access.
4. Slowest steps are those that require floating point register access.

 

17. What is the major drawback of Dynamic RAM (DRAM)?
    1. cost
    2. capacity
    3. data loss
    4. memory latency

 

18. Which of the following is a commonly used approach for improving performance of memory?

1. Doubling the capacity of memory.
2. Using DRAM instead of SDRAM.
3. Compressing instructions and data in RAM.
4. Widening the system bus between memory and the CPU.

 

19. Another method for increasing the effective rate of memory access is to divide memory into parts, called,                                      so that it is possible to access more than one location at a time.

1. block separation
2. high-low separation
3. memory interleaving
4. wide-path separation

 

20. Each block of cache memory provides a small amount of storage, perhaps between 8 and 64 bytes, also known as

1. a cache hit.
2. niche cache.
3. a cache line.
4. a small block cache.

 

21. What does "locality of reference" mean?

1. most memory references occur concurrently
2. most memory references will pull data of numeric type
3. most memory references will be accessed in a predictable order
4. most memory references are confined to one or a few small regions of memory

 

22. The locality of reference principal makes sense because most of the instructions being executed at a particular time are

1. register-to-memory type instructions.
2. math and logical type instructions.
3. control and branch type instructions.
4. part of a small loop or a small procedure or function.

 

23. Cache memory hit ratios of                            percent and above are common with just a small amount of cache.

1. 30
2. 60
3. 80
4. 90

 

24. When a cache miss occurs, however, there is a time delay while new data is moved to the cache. The time to move data to the cache is called                                         time.

1. stall
2. backup
3. write-through
4. cache back

 

25. Which of the following is most likely:

1. L1 cache has 32KB and L2 cache has 1MB
2. L1 cache has 1MB and L2 cache has 32KB
3. L1 cache has 32KB and L2 cache has 32KB
4. L1 cache has 1MB and L2 cache has 1MB

 

26. A part of main memory can be allocated to store several adjoining blocks of disk memory. If the requested data is in                           then no disk access is necessary.

1. disk cache
2. cache blocks
3. read once cache
4. buffer disk cache

 

27. Instructions, fetched from memory, are                                       within the instruction unit, to determine the type of instruction that is being executed. This allows branch instructions to be passed quickly to the branch processing unit for analysis of future instruction flow.

1. partially decoded
2. partially executed
3. completely decoded
4. completely executed

 

28. In a superscalar CPU, the instruction unit has a(n)                    to hold instructions until the required type of execution unit is available.

1. pipeline
2. assembly unit
3. instruction set
4. cache memory

 

29. Computers that have multiple CPUs within a single computer, sharing some or all of the system's memory and I/O facilities, are called                                           , or sometimes tightly coupled systems.

1. bundled systems
2. simultaneous systems
3. multiprocessor systems
4. compound processor systems

 

30. Under ideal conditions, each CPU processes its own assigned sequence of program instructions

1. independently of other CPUs.
2. partially sharing the workload with other CPUs.
3. without interrupting the other CPUs.
4. by sharing L1 cache between other CPUs.

 

31. Each CPU in the processor, within a single integrated chip, is called a                                           

1. core.
2. CPU unit.
3. control unit.
4. Independent Processor Chip (IPC).

 

32. Which of the following is not an advantage of adding more than one CPU processor within a single integrated chip?

1. Relatively inexpensive.
2. Reduce resource conflicts.
3. Programs can be divided into independent pieces and run separately.
4. Reduces power consumption, heat, and stress but gives equivalent processing power.

 

33. What is a "thread"?

1. The same segment of code used by many programs.
2. Independent segments of programs available to be executed in parallel.
3. The set of all variables that are used by all programs in execution.
4. Shared allocation of cache memory used by programs available to be executed.

 

34. In Symmetrical Multiprocessing (SMP) each CPU has

1. identical access to memory.
2. identical access to the I/O and memory.
3. identical access to the operating system, I/O and memory
4. identical access to the operating system, and to all system resources, including memory.

 

35. Simultaneous thread multiprocessing (STM) is also known as                                        

1. hyperthreading.
2. superthreading

3. expert threading
4. concurrent threading

 

Chapter 8 Discussion Questions

 

1. 1. What are common characteristics included in the instruction set architecture (ISA)?

 

 

1. 2. What are three important CPU architectural families, today?

 

 

1. 3. Having large numbers of specialized instructions inhibited efficient organization of the CPU. Why?

 

 

1. 4. What is the benefit of having fixed-length instructions over variable-length instructions?

 

 

1. 5. Describe the technique called code-morphing.

 

 

1. 6. Summarize how separating the fetch-execution cycle into different fetch and execution units improves performance.

 

 

1. 7. Summarize how pipelining improves performance.

 

 

1. 8. Summarize the performance benefits of using separate execution units for different types of instructions.

 

 

1. 9. Do pipelining and superscalar processing techniques affect the number of clock cycles of any individual instruction? Explain your answer.

 

 

 

1. 10. Superscalar processing complicates the design of a CPU considerably. There are a number of difficult technical issues that must be resolved to make it possible to execute multiple instructions simultaneously. What are the most important issues?

 

 

 

1. 11. How does the cache controller know when to use cache or go to main memory?

 

 

1. 12. Caching recently used data and instructions is an important performance enhancement. Summarize the benefits cache.

 

 

1. 13. If a cache block is altered, what methods are used to update main memory? Of the various methods, which is faster?

 

 

1. 14. Summarize the principle of “locality of reference”?

 

1. 15. Increasing the number of CPUs is usually an effective way to improve performance although, as the number of CPUs increases, the value of the additional CPUs diminishes. Why is that?