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Lab 3: VLSI System Design (Spring 2021) Design and implement an 8bit x 8bit Array Multiplier (Multiplier

Electrical Engineering

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Lab 3: VLSI System Design (Spring 2021)

Design and implement an 8bit x 8bit Array Multiplier (Multiplier.pdf file attached) using Magic, using basic gates from your Standard Cell gate library in 0.6 um technology.

The design should have Power and Ground (P/G) supply networks, and a zero skew Clock network.

Optimize the entire design for non-zero clock skew to maximize the clocking frequency.

Submit your gate library (along with the gate characteristic Table) .mag files, entire design (for different optimized versions) .mag files, IRSIM .sim files and results (for different optimized versions). These should be in a single directory — upload the compressed version of the directory on Canvas.

Part 1: The multiplication operation is UNPIPELINED.

Part 2: The multiplication operation is PIPELINED.

Points distribution (total 100):

Part1:

(a) Array Multiplier Unpipelined Layout (with P/G networks) = 25

(b) IRSIM results for (a) above = 10

Part 2:

(c) Array Multiplier Pipelined Layout (without clock network) = 25

(d) IRSIM results for (c) above for 20 clock cycles (a new pair of 8bit numbers is input to the multiplier in every clock cycle) = 10

(e) Array Multiplier Pipelined Layout (with zero skew clock network design) = 25

(f) IRSIM results for (e) above for 20 clock cycles (a new pair of 8bit numbers is input to the multiplier in every clock cycle) =5

Due Date: April 30