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Consider a processor with 2 cores namely P and Q, each with its own L1 D-Cache, sharing an L2 cache

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Consider a processor with 2 cores namely P and Q, each with its own L1 D-Cache, sharing an L2 cache. The caches adopt the MESI protocol with write allocate and write-back policies. Initially, both L1 caches are empty and the L2 cache contains a valid cache block with a tag X. (a) What are the possible states of the cache block with a tag X in the L2 cache? (2 marks) (b) At some point in time, Q reads a block with a tag X. (i) Explain whether cache hit or miss will be experienced in Q’s L1 cache? (2 marks) (ii) Will Q’s L1 send anything to the bus? If so, describe and explain what happens on the bus. (4 marks) (iii) What is the resulting state of the block in Q’s L1? (1 mark) (c) After the transaction in (b), P writes a DWORD to the block with a tag X. (i) When Q’s L1 snoops the bus, will Q’s L1 observe any activity on the bus as a result of the write by P? Describe and explain what happens. (4 marks) (ii) What is the resulting state of the block in P’s L1? (1 mark) (iii) Describe and explain what happens of the L2 cache. (2 marks) (d) Immediately after the transaction in (c), P writes a BYTE to the block with a tag X. (i) When Q’s L1 snoops the bus, will Q’s L1 observe any activity on the bus as a result of the write by P? Describe and explain what happens. (2 marks) (ii) What is the resulting state of the block in P’s L1? (1 mark) (e) Immediately after the transaction in (d), Q reads a BYTE from a block with a tag X. (i) Describe the sequence of events taking place next. (4 marks) (ii) What are the resulting states of the block in P’s L1 and Q’s L1, respectively? (2 marks) (f) Suppose the MESIF protocol is adopted (rather than MESI), (i) Will there be any difference in the answer of (a) to (e)? Describe and explain your answer. (2 marks) (ii) Will there be any improvement in performance? Describe and explain your answer.(3 marks)