ARMv7

ARMv7 is a popular 32-bit RISC-inspired ISA, and by far the most widely implemented architecture in the world [10]. As we weighed whether or not to design our own instruction set, ARMv7 was a natural alternative due to the great quantity of software that has been ported to the ISA and to its ubiquity in embedded and mobile devices. Ultimately, we could not adopt ARMv7 because it is a closed standard. Sub setting the ISA or extending it with new instructions is explicitly disallowed; even micro architectural innovation is restricted to those who can afford what ARM refers to as an architectural license. Had intellectual property encumbrances not been an issue, though, there are several technical deficiencies in ARMv7 that strongly disinclined us to use it:

• At the time, there was no support for 64-bit addresses, and the ISA lacked hardware support for the IEEE 754-2008 standard. (ARMv8 rectified these deficiencies, as discussed in the next section.)

• The details of the privileged architecture seep into the definition of the user-level architecture. This concern is not merely aesthetic. ARMv7 is not classically virtualizable [32] because, among other reasons, the return-from-exception instruction, RFE, is not defined to trap when executed in user mode [79, 8]. ARM has added a hypervisor privilege mode in recent revisions of the architecture, but as of this writing, it remains impossible to classically virtualize without dynamic binary translation.

• ARMv7 is packaged with a compressed ISA with fixed-width 16-bit instructions, called Thumb. Thumb offers competitive code size but low performance, especially on floatingpoint-intensive code. A variable-length instruction set, Thumb-2, followed later, providing much higher performance. Unfortunately, since Thumb-2 was conceived after the base ARMv7 ISA was defined, the 32-bit instructions in Thumb-2 are encoded differently than the 32-bit instructions in the base ISA. (The 16-bit instructions in Thumb-2 are also encoded differently than the 16-bit instructions in the original Thumb ISA.) Effectively, the instruction decoders need to understand three ISAs, adding to energy, latency, and design cost.

• The ISA has many features that complicate implementations. It is not a truly generalpurpose register architecture: the program counter is one of the addressable registers, meaning that nearly any instruction can change the flow of control. Worse yet, the least-significant bit of the program counter reflects which ISA is currently executing (ARM or Thumb)—the humble ADD instruction can change which ISA is currently executing on the processor! The use of condition codes for branches and predication further complicates high-performance implementations. ARMv7 is vast and complicated. Between ARM and Thumb, there are over 600 instructions in the integer ISA alone3 . NEON, the integer SIMD and floating-point extension, adds hundreds more. Even if it had been legally feasible for us to implement ARMv7, it would have been quite challenging technically.

OpenRISC

The OpenRISC sproject is an open-source processor design effort that evolved out of the educational DLX architecture of Hennessy and Patterson’s influential computer architecture textbook [39]. As a free and open ISA, OpenRISC is legally suitable for use in academic, research, and industrial implementations. Like the DLX, though, it has several technical drawbacks that limit its applicability:

• The OpenRISC project is principally an open processor design, rather than an open ISA specification. The ISA and implementation are very tightly coupled.

• The fixed 32-bit encoding with 16-bit immediates precludes a compressed ISA extension.

• The 2008 revision of the IEEE 754 standard is not supported in hardware.

• Condition codes, used for branches and conditional moves, complicate high-performance implementations.

• The ISA provides poor support for position-independent data addressing.

• OpenRISC is not classically virtualizable because the return-from-exception instruction, L.RFE, is defined to function normally in user mode, rather than trapping5 [72]. When we first investigated OpenRISC in 2010, the ISA had two additional drawbacks: mandatory branch delay slots, and no 64-bit address space variant. To the architects’ credit, both of these have been rectified: the delay slots have become optional, and the 64-bit version has been defined (but, to our knowledge, never implemented). Ultimately, we thought it was best for our purposes to start from a clean slate, rather than modifying OpenRISC accordingly.

Instructions:-

ARMv7

ARMv7 is a popular 32-bit RISC-inspired ISA, and by far the most widely implemented architecture in the world [10]. As we weighed whether or not to design our own instruction set, ARMv7 was a natural alternative due to the great quantity of software that has been ported to the ISA and to its ubiquity in embedded and mobile devices. Ultimately, we could not adopt ARMv7 because it is a closed standard. Sub setting the ISA or extending it with new instructions is explicitly disallowed; even micro architectural innovation is restricted to those who can afford what ARM refers to as an architectural license. Had intellectual property encumbrances not been an issue, though, there are several technical deficiencies in ARMv7 that strongly disinclined us to use it:

• At the time, there was no support for 64-bit addresses, and the ISA lacked hardware support for the IEEE 754-2008 standard. (ARMv8 rectified these deficiencies, as discussed in the next section.)

• The details of the privileged architecture seep into the definition of the user-level architecture. This concern is not merely aesthetic. ARMv7 is not classically virtualizable [32] because, among other reasons, the return-from-exception instruction, RFE, is not defined to trap when executed in user mode [79, 8]. ARM has added a hypervisor privilege mode in recent revisions of the architecture, but as of this writing, it remains impossible to classically virtualize without dynamic binary translation.

• ARMv7 is packaged with a compressed ISA with fixed-width 16-bit instructions, called Thumb. Thumb offers competitive code size but low performance, especially on floatingpoint-intensive code. A variable-length instruction set, Thumb-2, followed later, providing much higher performance. Unfortunately, since Thumb-2 was conceived after the base ARMv7 ISA was defined, the 32-bit instructions in Thumb-2 are encoded differently than the 32-bit instructions in the base ISA. (The 16-bit instructions in Thumb-2 are also encoded differently than the 16-bit instructions in the original Thumb ISA.) Effectively, the instruction decoders need to understand three ISAs, adding to energy, latency, and design cost.

• The ISA has many features that complicate implementations. It is not a truly generalpurpose register architecture: the program counter is one of the addressable registers, meaning that nearly any instruction can change the flow of control. Worse yet, the least-significant bit of the program counter reflects which ISA is currently executing (ARM or Thumb)—the humble ADD instruction can change which ISA is currently executing on the processor! The use of condition codes for branches and predication further complicates high-performance implementations. ARMv7 is vast and complicated. Between ARM and Thumb, there are over 600 instructions in the integer ISA alone3 . NEON, the integer SIMD and floating-point extension, adds hundreds more. Even if it had been legally feasible for us to implement ARMv7, it would have been quite challenging technically.

OpenRISC

The OpenRISC sproject is an open-source processor design effort that evolved out of the educational DLX architecture of Hennessy and Patterson’s influential computer architecture textbook [39]. As a free and open ISA, OpenRISC is legally suitable for use in academic, research, and industrial implementations. Like the DLX, though, it has several technical drawbacks that limit its applicability:

• The OpenRISC project is principally an open processor design, rather than an open ISA specification. The ISA and implementation are very tightly coupled.

• The fixed 32-bit encoding with 16-bit immediates precludes a compressed ISA extension.

• The 2008 revision of the IEEE 754 standard is not supported in hardware.

• Condition codes, used for branches and conditional moves, complicate high-performance implementations.

• The ISA provides poor support for position-independent data addressing.

• OpenRISC is not classically virtualizable because the return-from-exception instruction, L.RFE, is defined to function normally in user mode, rather than trapping5 [72]. When we first investigated OpenRISC in 2010, the ISA had two additional drawbacks: mandatory branch delay slots, and no 64-bit address space variant. To the architects’ credit, both of these have been rectified: the delay slots have become optional, and the 64-bit version has been defined (but, to our knowledge, never implemented). Ultimately, we thought it was best for our purposes to start from a clean slate, rather than modifying OpenRISC accordingly.

Instructions:-

ARMv7

ARMv7 is a popular 32-bit RISC-inspired ISA, and by far the most widely implemented architecture in the world [10]. As we weighed whether or not to design our own instruction set, ARMv7 was a natural alternative due to the great quantity of software that has been ported to the ISA and to its ubiquity in embedded and mobile devices. Ultimately, we could not adopt ARMv7 because it is a closed standard. Sub setting the ISA or extending it with new instructions is explicitly disallowed; even micro architectural innovation is restricted to those who can afford what ARM refers to as an architectural license. Had intellectual property encumbrances not been an issue, though, there are several technical deficiencies in ARMv7 that strongly disinclined us to use it:

• At the time, there was no support for 64-bit addresses, and the ISA lacked hardware support for the IEEE 754-2008 standard. (ARMv8 rectified these deficiencies, as discussed in the next section.)

• The details of the privileged architecture seep into the definition of the user-level architecture. This concern is not merely aesthetic. ARMv7 is not classically virtualizable [32] because, among other reasons, the return-from-exception instruction, RFE, is not defined to trap when executed in user mode [79, 8]. ARM has added a hypervisor privilege mode in recent revisions of the architecture, but as of this writing, it remains impossible to classically virtualize without dynamic binary translation.

• ARMv7 is packaged with a compressed ISA with fixed-width 16-bit instructions, called Thumb. Thumb offers competitive code size but low performance, especially on floatingpoint-intensive code. A variable-length instruction set, Thumb-2, followed later, providing much higher performance. Unfortunately, since Thumb-2 was conceived after the base ARMv7 ISA was defined, the 32-bit instructions in Thumb-2 are encoded differently than the 32-bit instructions in the base ISA. (The 16-bit instructions in Thumb-2 are also encoded differently than the 16-bit instructions in the original Thumb ISA.) Effectively, the instruction decoders need to understand three ISAs, adding to energy, latency, and design cost.

• The ISA has many features that complicate implementations. It is not a truly generalpurpose register architecture: the program counter is one of the addressable registers, meaning that nearly any instruction can change the flow of control. Worse yet, the least-significant bit of the program counter reflects which ISA is currently executing (ARM or Thumb)—the humble ADD instruction can change which ISA is currently executing on the processor! The use of condition codes for branches and predication further complicates high-performance implementations. ARMv7 is vast and complicated. Between ARM and Thumb, there are over 600 instructions in the integer ISA alone3 . NEON, the integer SIMD and floating-point extension, adds hundreds more. Even if it had been legally feasible for us to implement ARMv7, it would have been quite challenging technically.

OpenRISC

The OpenRISC sproject is an open-source processor design effort that evolved out of the educational DLX architecture of Hennessy and Patterson’s influential computer architecture textbook [39]. As a free and open ISA, OpenRISC is legally suitable for use in academic, research, and industrial implementations. Like the DLX, though, it has several technical drawbacks that limit its applicability:

• The OpenRISC project is principally an open processor design, rather than an open ISA specification. The ISA and implementation are very tightly coupled.

• The fixed 32-bit encoding with 16-bit immediates precludes a compressed ISA extension.

• The 2008 revision of the IEEE 754 standard is not supported in hardware.

• Condition codes, used for branches and conditional moves, complicate high-performance implementations.

• The ISA provides poor support for position-independent data addressing.

• OpenRISC is not classically virtualizable because the return-from-exception instruction, L.RFE, is defined to function normally in user mode, rather than trapping5 [72]. When we first investigated OpenRISC in 2010, the ISA had two additional drawbacks: mandatory branch delay slots, and no 64-bit address space variant. To the architects’ credit, both of these have been rectified: the delay slots have become optional, and the 64-bit version has been defined (but, to our knowledge, never implemented). Ultimately, we thought it was best for our purposes to start from a clean slate, rather than modifying OpenRISC accordingly.

Instructions:- ARMv7 ARMv7 is a popular 32-bit RISC-inspired ISA, and by far the most widely implemented architecture in the world [10]. As we weighed whether or not to design our own instruction set, ARMv7 was a natural alternative due to the great quantity of software that has been ported to the ISA and to its ubiquity in embedded and mobile devices. Ultimately, we could not adopt ARMv7 because it is a closed standard. Sub setting the ISA or extending it with new instructions is explicitly disallowed; even micro architectural innovation is restricted to those who can afford what ARM refers to as an architectural license. Had intellectual property encumbrances not been an issue, though, there are several technical deficiencies in ARMv7 that strongly disinclined us to use it: • At the time, there was no support for 64-bit addresses, and the ISA lacked hardware support for the IEEE 754-2008 standard. (ARMv8 rectified these deficiencies, as discussed in the next section.) • The details of the privileged architecture seep into the definition of the user-level architecture. This concern is not merely aesthetic. ARMv7 is not classically virtualizable [32] because, among other reasons, the return-from-exception instruction, RFE, is not defined to trap when executed in user mode [79, 8]. ARM has added a hypervisor privilege mode in recent revisions of the architecture, but as of this writing, it remains impossible to classically virtualize without dynamic binary translation. • ARMv7 is packaged with a compressed ISA with fixed-width 16-bit instructions, called Thumb. Thumb offers competitive code size but low performance, especially on floatingpoint-intensive code. A variable-length instruction set, Thumb-2, followed later, providing much higher performance. Unfortunately, since Thumb-2 was conceived after the base ARMv7 ISA was defined, the 32-bit instructions in Thumb-2 are encoded differently than the 32-bit instructions in the base ISA. (The 16-bit instructions in Thumb-2 are also encoded differently than the 16-bit instructions in the original Thumb ISA.) Effectively, the instruction decoders need to understand three ISAs, adding to energy, latency, and design cost. • The ISA has many features that complicate implementations. It is not a truly generalpurpose register architecture: the program counter is one of the addressable registers, meaning that nearly any instruction can change the flow of control. Worse yet, the least-significant bit of the program counter reflects which ISA is currently executing (ARM or Thumb)—the humble ADD instruction can change which ISA is currently executing on the processor! The use of condition codes for branches and predication further complicates high-performance implementations. ARMv7 is vast and complicated. Between ARM and Thumb, there are over 600 instructions in the integer ISA alone3 . NEON, the integer SIMD and floating-point extension, adds hundreds more. Even if it had been legally feasible for us to implement ARMv7, it would have been quite challenging technically. OpenRISC The OpenRISC sproject is an open-source processor design effort that evolved out of the educational DLX architecture of Hennessy and Patterson’s influential computer architecture textbook [39]. As a free and open ISA, OpenRISC is legally suitable for use in academic, research, and industrial implementations. Like the DLX, though, it has several technical drawbacks that limit its applicability: • The OpenRISC project is principally an open processor design, rather than an open ISA specification. The ISA and implementation are very tightly coupled. • The fixed 32-bit encoding with 16-bit immediates precludes a compressed ISA extension. • The 2008 revision of the IEEE 754 standard is not supported in hardware. • Condition codes, used for branches and conditional moves, complicate high-performance implementations. • The ISA provides poor support for position-independent data addressing. • OpenRISC is not classically virtualizable because the return-from-exception instruction, L.RFE, is defined to function normally in user mode, rather than trapping5 [72]. When we first investigated OpenRISC in 2010, the ISA had two additional drawbacks: mandatory branch delay slots, and no 64-bit address space variant. To the architects’ credit, both of these have been rectified: the delay slots have become optional, and the 64-bit version has been defined (but, to our knowledge, never implemented). Ultimately, we thought it was best for our purposes to start from a clean slate, rather than modifying OpenRISC accordingly.