Which of the following sequences of RISC-V instructions would correctly mask off all but bits 24-20 (i

Which of the following sequences of RISC-V instructions would correctly mask off all but bits 24-20 (i.e., set all other bits to zero) of the value in register x18? Keep in mind that immediate values in instructions are limited to 12 bits. (Check all that apply)
A) andi  x18, x18, 0x1f00000


B) slli  x18, x18, 39
srli  x18, x18, 59
slli  x18, x18, 20


C) addi  x5, x0, 0x1f
slli   x5, x5, 20
and  x18, x18, x5


D) addi  x5, x0, 0x1f
slli   x5, x5, 20
or    x18, x18, x5


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