Can you please advise me on what a Preliminary Design Model, and a Logical Model of the System are

please see the attached file.

1. Proliminary Design Model:
At the very start of the design process, the problem statement is very carefully analyzed, and a requirements list is prepared. Often times, the system analyst must work closely with the requester (customer) to understand the problem, because problem statements are rarely complete. From the initial set of requirements, a set of derived requirements must be prepared. It is the purpose of the analyst to make the problem statement more precise and to expose ambiguities and inconsistancies. The problem statement should not be considered unchangeable but should serve as the foundation to which to build upon. The analyst now builds a preliminary design model. At this stage the model is concise: a precise abstraction of what rather than how. There is no scope for implementation details at this point. This model is presented to other system analysts where it is reviewed, criticized, and refined.

2. Logical Design Model
The model is now subdivided into logical and physical subsystems based on the proposed architecture. This subdivision is made on a functional and behavioral basis. The logical part is the logical design model. Each subsystem encompasses aspects of the system that share some common properties such as same basic functions, proximity of physical location, or the same basic hardware. For example, a robotic paint stripping system might consist subsystems for vision, mapping, paint removal, etc. A subsystem may also be divided into other subsystems, and thus a heirarchy of subsystems may be obtained. Various performance issues are now considered, optimized, and trade-offs are made. At this point, details are added to the subsystems and a design model based on the analysis model is prepared. Issues such as compatibility and interfacing between the subsystems, and the integration of each independent subsystem into a fully functional system are considered. Subsystems are defined so that most interactions are within the subsystems, rather than across the subsystems. This reduces dependancies, and facilitates future modifications and maintenance. Each of these subsytems are representative of a system object.

An Example

For example, consider the implementation of a very preliminary microprocessor with a limited instruction set and on-chip RAM. The first step would be to determine the instruction set required. This would also dictate the minimum bit width (N). The amount of on-chip RAM required must also be known. As seen in the VHDL source code defining these parameters in a package allows us to make changes and implement them just by recompiling the source code. Next, the inputs and outputs of the microprocessor are determined. A clock (CLK) input is used by the microprocessor to generate the internal timing for the different operations. A reset (Reset, active high) input resets the microprocessor. A separate program memory reset (PMReset, active high) is provided to reset the memory, so that the same program may be used over and over again. A program pulse (ProgPulse, positive edge triggered) input along with a program enable (Prog, active high) input is used to program the memory. The data inputs (DIN(0) to DIN(N-1)) are set to the data store in the memory each time the program pulse is given with program mode enabled. The system outputs consist of an error (Error) output indicating an error condition such as an invalid instruction, and outputs (Out(0) to Out(N-1)).

Once all the requirements (or, most of them) have been determined, the preliminary design model is defined.

The model is now subdivided into logical subsystems, which are combined to define the logical design model. In our case the microprocessor has been divided into five system objects :
• Timing Generation
• Fetch And Decode
• Execute
• Memory
• Heart

In the VHDL source code each system object is represented by an entity and an architecture body. The timing generation system object gets the external clock signal, and generates the states t0 to t3. The fetch and decode system object fetches the next instruction from the program memory, and decodes it during the t0 state. The execution system object executes the decoded instruction during the t3 state, and also fetches any immediate operands if required. The memory system object keeps track of the current memory location to be accessed, and updates the program counter during every t1 state and also during t3 if necessary. It is also responsible for loading an external program when the program mode is enabled and program pulse is received. The heart system object instantiates all the components (when entities are used by another entity they are called components). and coordinates all the activities. This action is similar to a parent object constructing objects.