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SRAM Write Problem 3 (20 pts

Electrical Engineering

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SRAM Write

Problem 3 (20 pts. HAND, 10 pts. SPICE):

Consider the following SRAM circuit with pre-charge and write circuitry with 130nm process parameters: • WP/L = 2.4 for all PMOS • WN/L = 1 for T3, T4, T5, T6 • WN/L = 10 for T9, T10 • L = 100nm • VDD = 1.2V

a) Identify the transistors that would pass current to perform a write of logic 1 to the SRAM cell.

b) Assuming a successful write of logic 1, what states would these transistors be in? c) Assuming a failed write of logic 1 (the transistors cannot pull Q, Q? below VDD/2):

i. What states would the transistors responsible for a write of logic 1 be in?

ii. Solve by hand the voltage obtained at node Q?. Assume BL???? = 0.

iii. Simulate this failed write in LTSpice. iv. In LTSpice, modify transistor widths so that a functional write is obtained. What transistor widths did you modify, and why?

Submit your work on LMS under Final • Show your work. • Include images of your hand calculations with work and final results. • Include screenshots of LTspice with all circuit schematics with all output plots. • Due date: Tuesday, May 4th at 11:59pm.