UNIVERSITY OF LIVERPOOL Department of Electrical Engineering and Electronics ELEC143 Coursework Design of a two-stage inverter chain Module ELEC143 Coursework name Design of a two-stage inverter chain Component weight 15% Semester 2 HE Level 4 Lab location N/A Work Individual Timetabled time 0 hours Suggested private study 24 hours (preparation and report writing) Assessment method Individual, formal word-processed report Submission format Online via Canvas (anonymous) Submission deadline Week 9: Friday 30th April 2021 Late submission Standard University penalty applies Resit opportunity August resit period via resit exams Marketing policy Marked and moderated independently Anonymous marking Yes Feedback Via Canvas Subject of relevance Inverter designs and layouts, MOSFET models Learning outcomes (LO4) Understanding of the application of the physical laws of semiconductor to practical silicon electronic devices (transistors)

Question

UNIVERSITY OF LIVERPOOL

Department of Electrical Engineering and Electronics

ELEC143 Coursework

Design of a two-stage inverter chain

Module	ELEC143
Coursework name	Design of a two-stage inverter chain
Component weight	15%
Semester	2
HE Level	4
Lab location	N/A
Work	Individual
Timetabled time	0 hours
Suggested private study	24 hours (preparation and report writing)
Assessment method	Individual, formal word-processed report
Submission format	Online via Canvas (anonymous)
Submission deadline	Week 9: Friday 30^th April 2021
Late submission	Standard University penalty applies
Resit opportunity	August resit period via resit exams
Marketing policy	Marked and moderated independently
Anonymous marking	Yes
Feedback	Via Canvas
Subject of relevance	Inverter designs and layouts, MOSFET models
Learning outcomes	(LO4) Understanding of the application of the physical laws of semiconductor to practical silicon electronic devices (transistors). (LO5) Familiarity of the common design rules for development of layouts for silicon devices and simple circuits (S1) Ability to show experience and enhancement of the following skills i.e. independent learning; problem solving and design skills.

Marking Criteria

Section	Marks available	Indicative characteristics Adequate / pass Very good / Excellent
Section	Marks available	(40%)	(> 40%)
Report presentation and structure	10%	Contains cover page information, table of contents, sections with appropriate headings. Comprehensible language; punctuation, grammar and spelling accurate. Equations legible, numbered and presented correctly. Appropriately formatted reference list.	Word-processed with consistent formatting. All sections clearly signposted. Pages numbered, and figures and tables captioned appropriately. Appropriate use of technical, mathematic and academic terminology and principles. Correct cross-referencing (of figures, tables, equations) and citations. Appropriate use of references and format. Appendix containing any additional evidence i.e. further results, graphs, photographs etc.
Introduction, Method and Calculations	30%	Problem background introduced clearly and objectives correctly presented. Appropriate methodology used in calculating the aspect ratio of all devices. Justification of any assumptions made. Aspect ratio of all devices correctly presented in terms of minimum feature size.	All calculations shown in full. All devices are correctly calculated. Summary table of the calculated aspect ratio presented in terms of minimum feature size. Design decisions are justified using at least one external source. Further justification and explanation of any assumptions made.
Device and circuit layouts	40%	Individual device layouts are correctly presented. Different regions within respective layout is easily distinguishable. Appropriate scale is defined. Results from each layout is accompanied by appropriate commentary.	All device layouts are correctly presented in terms of the minimum feature size. Appropriate alignment accuracy is included within respective layouts. Overall circuit layout is correctly presented, i.e. correct connections, including interconnects and contact pads. Minimal area is utilised in the circuit layout arrangement.
Discussions and Conclusion	20%	Basic discussion demonstrating an understanding of the underlying concepts. Conclusions correctly inferred from the calculation, results and layouts. Evidence of wider reading. Evidence of basic reflection and self-criticism.	Thorough analysis is presented, including justification on the selection of aspect ratios and area minimisation. Meaningful reflection on the limitations work, and insight into possible realistic improvements.

Overview: The aim of this coursework is to design a two-stage inverter circuit, as shown in Fig.1. This will initially involve calculating respective dimensions of the different devices within the circuit (i.e. MOSFETs A, B, and C, and passive load _ resistor R_L) using appropriate models or equations, and Vin parameters and constants provided below. Subsequently, respective layouts for each of the devices, and an overall circuit, including interconnects and contact pads, needs to be generated accurately, on scaled or graph paper/s with stipulated scale (e.g. 1 mm = 1 cm). Accurate alignment error between layouts must also be included with minimal area utilised. All of the dimensions/areas of the layouts must be expressed in terms of the minimum feature size (l_m).

V_DD

C R_L

V₀^’V_out

A B

V_in

Fig. 1

Description: The circuit in Fig. 1 consists of two-stage inverters (NOT gates), with respective input V_in and output V_out. The first stage of the inverter consists of an enhancement n-MOS transistor A (driver) and a saturated n-MOS transistor C (load), whilst the second stage consists of an enhancement n-MOS transistor B (driver) with a passive load R_L. In terms of operation, the logic at the output follows the logic at the input after some delay, i.e. if V_in is at logic 1 then V_out is logic 1 and vice versa. This circuit forms part of a ring oscillator, which typically comprises of odd number of inverters, connected in a loop as discussed in ELEC143. The output oscillates between two logic levels, and commonly used to determine gate delays or operation speeds of circuits. However, for this coursework, the main objective is to understand and implement methods for generating and representing circuit layouts appropriately with effective use of area as discussed in ELEC148. This will also allow to make comparison/s on the area (size) used for different the devices e.g. active MOS load (C) against passive load (RL).

Useful hints

1. Focus on the first-stage inverter (i.e. driver A and load C) and determine the respective aspect ratios (W/L) of the transistors. Assuming a logic 1 input into A (i.e. transistor is on), the intermediate output V₀^’ is a logic 0. This logic is then fed into the input of the second inverter. You will need to select an appropriate value for this output voltage V₀^’ corresponding to a logic 0. Note this needs to be lower than the threshold voltage of the driver B so as to ensure that B remains off at logic 0 input. In addition, load C is always on and operating in saturation. Refer to ELEC143 lecture notes on the MOSFET and inverter operations.

2. The resistance of A is can be assumed to be the same as the resistance of B, when the transistors are on. Similarly, the resistance of C can be assumed to be equal to that of R_L. However, the dimension of C is not the same as RL since these are different devices. Refer to ELEC143 notes on p-n junction (passive load) to determine the dimensions for R_L, assuming sheet resistance value given below.

3. The layouts must take into account the alignment accuracy (la), which can be assumed to be equal to the minimum feature size lm or multiple of lm.

Parameter/constants: Below are respective values for use in the calculation:

i. Minimum feature size, lm = 0.5 mm

ii. Supply voltage, V_DD = 5 V (Logic 1 input)

iii. Threshold voltage of the transistors, V_T = 0.3 V

iv. Sheet resistance for the load resistor, R_sheet = 100 W/square

v. Device constant is given as below:

b = (mC₀) W/L = (b₀) W/L

Note: The mobility m and gate capacitance C₀ can be assumed to be the same for all transistors, i.e. b₀ = 1.8 x 10^-4 AV^-2.

Report: Individual report should include ALL of your calculations and justify any assumption made. The report must also include individual design layouts of all the devices and an overall design layout of the circuit in Fig. 1, including interconnects and contact pads on scaled graph papers. The layouts must be expressed in terms of the minimum feature size with appropriate alignment errors. Different shading should be used to differentiate regions of the respective layouts. The area should also be utilised effectively on the overall layout. The deadline for the report is Friday 30^th April 2021 by 23:59 on Canvas.