Consider a synchronous circuit where every clock cycle an n—bit RCA adder (section 15

Consider a synchronous circuit where every clock cycle an n—bit RCA adder (section 15.2) is used to increment (+1) an n-bit register value. This circuit contains an n-bit RCA adder, an n-bit register, and the hard-wired input of the n-bit binary representation of the constant value one. a) Draw a circuit diagram for the case n=8. b) Consider that in the Motorola delay model the delay for a full adder is 6 inverter delays and the delay for a ?ip-?op is 5 (setup time plus propagation delay). What is the delay on the critical path for this circuit a. for n=8? b. in dependency of n? c) What is the highest clock ?equency that can be used for this circuit if an inverter delay is 10 ps = 10'11 seconds for our technology a. For n=8? b. For n=32? c. For n=64?