Machine A is single-cycle with 50 nsec cycle time

Machine A is single-cycle with 50 nsec cycle time. Machine B is 5-stage pipelined at 10 nsec per stage. The latency of the instructions executed in Machine A and Machine B are the same, ignoring the sequencing timing overhead. O True False Consider the MIPS byte addressable data memory with 32 bits address. Assume the cache capacity is 256K words (not including tag and valid bits). Each cache block contains 4 words. Based on these assumptions, is this true or false? : In four-way set associative configuration, cache index is 13 bits and tag bits is 12 bits. True O False Assume a direct-mapped MIPS memory has 64 words and a cache has 8 words and each word is 4 bytes. The number of bits for "Set" is 3. o True O False Layer-1 cache is implemented in SRAM and is built into the fabric of the processor core and operates at the same clock rate. True O False